1. Field of the Invention
The present invention relates to the field of signal modulation and, more particularly, to the qualification of signals in an optical disc apparatus.
2. Description of the Related Art
As part of the process of recording or reproducing digital signals, a modulator converts an input analog signal into digital code suitable for the characteristics of a recording/reproducing system. This conversion is known as channel coding. In a conventional optical disc playback apparatus, modulated signals contain an average DC voltage component equal to zero (known as xe2x80x9cDC-freexe2x80x9d code) and the long term average duty cycle is typically specified as 50%.
In some conventional optical disc systems such as Compact Disk (CD) and Digital Versatile Discxe2x80x94Read Only Memory (DVD-ROM), a duty cycle detection feedback method is commonly employed for data qualification during the processing of digital signals. This method relies on the xe2x80x9cDC-freexe2x80x9d nature of the code. The basic approach of this method is to monitor the DC content of the digital data using a threshold detector, and to control the threshold level until a 50% duty cycle is achieved in the digital stream.
For example, in typical CD systems, signal modulation is performed according to the Eight-to-Fourteen Modulation (EFM) code protocol. In EFM, an 8-bit input code is converted into a 14-bit channel code by an encoder. However, the encoder uses only 28 of all possible 14-bit words of which there are 214. In particular, only those 14-bit words which satisfy a (2,10) run length constraint are used. The designation (2,10) means that there are at least two zeros, and no more than ten zeros, between successive 1""s in the digital stream of data comprised of these encoded 14-bit word. Since there are at least 2 and not more than 10 xe2x80x9c0xe2x80x9ds between two consecutive xe2x80x9c1xe2x80x9ds, a period (or wavelength) of a low level or a high level Non return to Zero Inverted (NRZ-I) waveform is always between 3T and 11T, where T is defined as one period of the channel clock. Therefore, under this protocol a 100100 (3T/3T) signal corresponds to the highest channel frequency and a 1000000000010000000000 (11T/11T) signal corresponds to the lowest channel frequency. The EFM encoder also adds 3 additional merging or linking bits between each consecutive 14-bit word encoded word to force the average duty cycle of the digital stream to the specified 50%, and to eliminate run-length violations where successive code words are linked serially. Where long term duty cycles of 50% are specified and maintained, the code is then considered to be xe2x80x9cDC-free.xe2x80x9d
In conventional DVD systems, such as in DVD-ROM systems, EFM Plus (eight-to-sixteen) code protocol is used for signal modulation. In the EFM Plus protocol, an 8-bit input code is converted into a 16-bit channel code by an encoder. As in the CD system described above, the EFM Plus encoder also generates (2,10) run length limited (RLL) code for use in conventional DVD-ROM systems. DC component suppression in a conventional DVD system, however, is controlled by four selectable DC component suppression (DCC) algorithms contained in the system.
In both the EFM protocol used in conventional CD systems and the EFM Plus protocol used in conventional DVD-ROM systems, the duty cycle correction or slicing schemes utilize the xe2x80x9cDC-freexe2x80x9d nature of the code. Therefore both the EFM and EFM Plus modulation protocols as implemented in CD and DVD-ROM systems result in signals that are free of DC components. In other words, the Digital Sum Value (DSV) of these data signals over the long term is zero. As is well known in the art, DSV is the summed value of the data in which a xe2x80x9chigh levelxe2x80x9d is defined as a xe2x80x9c+1xe2x80x9d signal and a xe2x80x9clow levelxe2x80x9d is defined as a xe2x80x9cxe2x88x921xe2x80x9d signal. Thus, for a stream of NRZ-I encoded digital data, DSV=(high level period)xc3x97(+1)+(low level period)xc3x97(xe2x88x921).
The long term summation of DSV, and correspondingly, of the DC components, is zero in xe2x80x9cDC-freexe2x80x9d code, because, the result of summing xe2x80x9c+1xe2x80x9d and xe2x80x9cxe2x88x921xe2x80x9d data values over a 50% duty cycle period is equal to zero. This prior art duty cycle detection feedback or slicing method can be used as long as the modulated signal remains DC-free and does not contain DC components. According to this method, asymmetry in the modulated digital signal is easily cancelled by using a negative feedback loop, since the data stored on the disc does not include DC components. A typical duty cycle detection feedback control loop to perform the slicing function has a low bandwidth, typically in the tens of kHz range.
The duty cycle detection feedback method described above is effective only when DC free code is used. When the data contains DC components (or the DSV is not equal to zero), however, the duty cycle detection feedback method cannot compensate for non-zero DSV since the slice level is fixed and limited by the AC ground level.
Non-zero DSV can occur in some DVD systems such as a DVD-RAM system. In DVD-RAM systems, the signal modulation code follows the EFM Plus protocol, similar to that of a DVD-ROM system, to maintain compatibility with DVD-ROM systems. The (2,10) RLL codes similar to those found in DVD-ROM systems and described above are also used. However, in DVD-RAM systems, data is usually written in Error Correction Code (ECC) block sizes of 32 kbytes. The DC component suppression control algorithms found in DVD-ROM systems would typically process the written data to limit DC components over the long term to zero. In a DVD-RAM application, however, limitations in the computational capability of algorithms of the type found in DVD-ROM systems, such as limitations in buffer size, result in some DSV variation and the presence of DC components in the resultant signal. When such a condition occurs, the conventional duty cycle detection feedback slicing method is inadequate, since the slice level cannot be adjusted to compensate for the presence of DC components. For example, in an instance where an initial data stream is 00/01/02/03 (Hex, 4bytes), the data is modulated to:
0010000000001001001000000001001000100001001000000100010010000000.
The DSV summation for this stream is:xe2x88x922+10xe2x88x923+3xe2x88x929+3xe2x88x924+5xe2x88x923+7xe2x88x924+3xe2x88x928=xe2x88x922. In another example, where the data stream is 5C/FE/5C/FE (Hex, 4 bytes), the data is modulated to:
0010000100001000100100000001000001000000000100010000001001000100.
The DSV summation of this stream xe2x88x922+5xe2x88x925+4xe2x88x923+8xe2x88x926+10xe2x88x924+7xe2x88x923+4xe2x88x923=+12. When these example data streams occur recursively or are repeated, the DSV summation over the long term varies from zero, DC components result, and the effective slice level differs from the AC ground level. When such a condition exists, the conventional duty cycle detection feedback method is inadequate and a method that performs slicing that is adaptable to variations in DSV is required.
Accordingly, the present invention is directed to a method and apparatus for adapting the signal slice level during data qualification in an optical disc apparatus to DSV variation, and also for substantially obviating one or more of the problems due to the limitations and disadvantages associated with the conventional duty cycle detection feedback method.
According to this method, phase error signals from a Phase Locked Loop (PLL) subjected to an input data signal are used to generate Pump Up (PU) and Pump Down (PD) signals. These signals are used to determine a direction and degree of a slice level shift and to control a voltage adjustment, through the use of feedback, of the modulated input analog signal to compensate for the slice level shift. The present invention also adapts to the presence of non-zero DSV, (or DC components) by generating phase error signals (also by the PLL) when DC components (and corresponding DSV variation) are detected. When DC components are detected, slice level shift is cancelled. In this manner, the method suppresses a system response to any effects of DC component variation and thereby adapts to their presence.
It is to be understood that both the foregoing general description and the following detailed description are merely exemplary and explanatory in nature and are intended to provide further explanation of the present invention as claimed.